Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to an integrated circuit, and more particularly, to an application processor for changing a clock signal used in an integrated circuit into a clock signal of an oscillator using a hardware power management unit when the integrated circuit is in system idle and devices including the same.
Dynamic voltage and frequency scaling (DVFS) is a technique whereby an operating frequency and an operation voltage are dynamically adjusted. Electronic systems can reduce unnecessary power consumption using DVFS. In most commonly used DVFS, the usage of a target circuit is periodically checked and an operating frequency and voltage applied to the target circuit are adjusted according to the check result to reduce unnecessary power consumption of the target circuit.
DVFS performed based on a result of checking the usage of a target circuit during the operation of an electronic system including the target circuit can reduce current consumption at the electronic system to some extent and sustain the performance of the electronic system. However, when DVFS is performed based on the result of checking the usage of the target circuit while the electronic system is in a system idle state, DVFS itself adversely affects current consumption at the electronic system. Recently, a system on chip (SoC) supports a low-power mode in order to increase the use time of batteries. When a central processing unit (CPU) periodically wakes up in a SoC using the low-power mode in order to perform DVFS, power consumption of the CPU takes a significantly large part of the entire power consumption of the SoC.